1. Field of the Invention
The present invention relates to a layered chip package including a plurality of chips stacked, and to a method of manufacturing the same.
2. Description of the Related Art
In recent years, a reduction in weight and an improvement in performance have been demanded of mobile devices typified by cellular phones and notebook personal computers. Accordingly, there has been a demand for higher integration of electronic components for use in mobile devices. Higher integration of electronic components has been demanded also for achieving an increase in capacity of semiconductor memory.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of chips, has attracting attention in recent years. In the present application, a package including a plurality of chips stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing a higher operation speed for a circuit and a reduction in stray capacitance of wiring, as well as the advantage of allowing higher integration.
Major examples of three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. According to the wire bonding method, a plurality of chips are stacked on a substrate and a plurality of electrodes formed on each chip are connected, by wire bonding, to external connecting terminals formed on the substrate. According to the through electrode method, a plurality of through electrodes are formed in each of chips to be stacked and inter-chip wiring is performed through the use of the through electrodes.
The wire bonding method has a problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between wires, and a problem that high resistances of the wires hamper a high-speed operation of a circuit.
The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that will be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; forming a plurality of through electrodes by filling the plurality of holes with metal such as Cu by plating; and removing unwanted portions of the seed layer.
According to the through electrode method, the through electrodes are formed by filling metal into holes having relatively high aspect ratios. Consequently, voids or keyholes are prone to occur in the through electrodes due to poor filling of the holes with metal, so that the reliability of wiring formed by the through electrodes tends to be reduced.
According to the through electrode method, an upper chip and a lower chip are physically joined to each other by connecting the through electrodes of the upper and lower chips by means of, for example, soldering. The through electrode method therefore requires that the upper and lower chips be accurately aligned and then joined to each other at high temperatures. When the upper and lower chips are joined to each other at high temperatures, however, misalignment between the upper and lower chips can occur due to expansion and contraction of the chips, which often results in electrical connection failure between the upper and lower chips.
U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In this method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced to form a plurality of structures each called a neo-chip. Each neo-chip includes: one or more chips; resin surrounding the chip(s); and a plurality of leads. The plurality of leads connected to each chip each have an end face exposed at a side surface of the neo-chip. Next, a plurality of kinds of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed at the same side surface of the stack.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.
The manufacturing method disclosed in U.S. Pat. No. 5,953,588 involves a number of process steps and this raises the cost for the layered chip package. According to this method, after the plurality of chips cut out from a processed wafer are embedded into the embedding resin, the plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer, as described above. Accurate alignment of the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package.
U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. According to this multilayer module, however, it is impossible to increase the proportion of the area occupied by the electronic element in each active layer, and consequently it is difficult to achieve higher integration.
For a wafer to be cut into a plurality of chips, the yield of the chips, that is, the rate of non-defective chips with respect to all chips obtained from the wafer, is 90% to 99% in many cases. Since a layered chip package includes a plurality of chips, the rate of layered chip packages in which all of the plurality of chips are non-defective is lower than the yield of the chips. The larger the number of chips included in each layered chip package, the lower the rate of layered chip packages in which all of the chips are non-defective.
A case will now be considered where a memory device such as a flash memory is formed using a layered chip package. In general, a redundancy technique of replacing a defective column of memory cells with a redundant column of memory cells is employed in a memory device such as a flash memory so that the memory device can normally function even when some memory cells are defective. In the case where a memory device is formed using a layered chip package, the redundancy technique is also employable to make it possible that, even if some of memory cells included in any chip are defective, the memory device can normally function while using the chip including the defective memory cells. However, if, for example, a chip that includes a control circuit and a plurality of memory cells has become defective due to a wiring failure in the control circuit and cannot function normally even by employing the redundancy technique, this defective chip is unusable. In this case, replacing the defective chip with a non-defective one raises the cost for the layered chip package.
US 2007/0165461 A1 discloses a technique of identifying one or more defective flash memory dies in a flash memory device having a plurality of flash memory dies, and disabling memory access operations to each identified die.
The technique disclosed in US 2007/0165461 A1 is applicable to the case where a memory device is formed using a layered chip package, so that one or more defective chips included in the layered chip package can be identified and disabled.
However, disabling a defective chip in a layered chip package involves a problem as described below. A layered chip package has wiring for connecting each chip to a plurality of terminals of the layered chip package. Even if a defective chip is disabled, there exists wiring that connects the defective chip to a plurality of terminals of the layered chip package. The wiring connecting the defective chip to the plurality of terminals of the layered chip package generates a capacitance or inductance that is unwanted for a device implemented by the layered chip package, such as a memory device, and/or generates a stray capacitance between itself and other wiring connected to non-defective chips. This is a hindrance to increasing the operation speed of the device such as the memory device.
In addition, if a layered chip package including a predetermined number of chips is able to implement a memory device having a desired memory capacity when all the chips included in the layered chip package are non-defective, it is impossible to implement the memory device having the desired memory capacity by simply disabling a defective chip included in the layered chip package.